Coherent
compute
fabric.
UCIe D2D, NC-NOC, IOMMU, L3/SLC, and the UCIe D2D interface (partner) that binds all three silicon units: the full interconnect and cache subsystem for your AI or RISC-V SoC compute silicon.
Every IP block
in the compute silicon.
Six distinct IP blocks from SignatureIP, plus RISC-V / CPU processor cores from ecosystem partners, form the complete Compute chiplet. Designed together, integrated by iNoCulator, signed off with Siemens Questa.
Coherent NoC (C-Noc)
The central coherent interconnect backbone for CPU/GPU cores, AI accelerators, and HBM controllers. CHI Rev E.b compliant, supporting full cache coherency across all masters.
- CHI Rev E.b protocol support
- Mesh and ring topology options
- Configurable bandwidth, latency, and QoS
- RTL generated by iNoCulator™
- Siemens Questa sign-off · SystemC/QEMU flows
- Arm and RISC-V processor compatible
Non-coherent NoC (NC-NOC)
Lightweight non-coherent fabric for IO peripherals, DMA engines, and subsystem controllers that don't require full cache coherency; optimized for area and power.
- Configurable bus widths and topology
- Low-latency, power-optimized design
- AXI4 / AXI4-Lite interface compatible
- Shares iNoCulator toolchain with C-Noc
- Bridges to C-Noc via CHI-AXI protocol bridge
IOMMU
Input/Output Memory Management Unit providing address translation, memory protection, and DMA access control for peripheral devices connected to the NoC fabric.
- Two-stage address translation (S1 + S2)
- SMMUv3 architecture compatible
- TLB and page-table walk hardware
- Fault reporting to hypervisor / OS
- Integrated directly into NoC slave ports
System-level cache (L3 / SLC)
Last-level shared cache providing high bandwidth between CPU clusters, AI accelerators, and main memory. Reduces off-chip traffic and latency across heterogeneous compute tiles.
- Configurable size: 4 MB to 32 MB+
- N-WAY set-associative, configurable
- Stash transactions for prefetch flows
- Integrated proxy cache for IO coherency
- CHI compliant; attaches to C-Noc HN-F port
Protocol bridges
The integration glue that connects heterogeneous IP blocks across different bus protocols, enabling Arm, RISC-V, and custom accelerators to coexist on a single compute silicon.
- CHI-AXI bridge (CHI master ↔ AXI slave)
- CHI-CPI bridge (cross-socket CHI)
- AXI4-SFI bridge (Arm Scalable Fabric Interface)
- Configurable data widths and ID widths
- All bridges validated against SigIP NoC IP
UCIe D2D interface (partner)
The chip-to-chip interface that connects the Compute chiplet to the IO chiplet over UCIe. The UCIe D2D gateway (partner) with UCIe D2D interface is a SignatureIP block, meaning you get a single vendor for the full D2D link from both sides.
- UCIe standard-compliant adapter
- UCIe chip-to-chip interface
- Configurable channel width and speed
- End-to-end from Compute to IO chiplet
- Minimal latency short-reach D2D link
- Validated UCIe D2D interface (partner) on IO chiplet too
From topology to
taped-out silicon.
Define NoC requirements in iNoCulator
Configure masters, slaves, memory map, coherent groups, and QoS targets in our browser-based design interface.
Generate & Simulate
iNoCulator generates complete C-Noc and NC-NOC SystemC models for instant virtual prototyping. Validate cycle-approximate latency and bandwidth matrices.
Questa Sign-Off Verification
Export production-ready, synthesizable SystemVerilog RTL. Compile and verify in Siemens Questa with pre-configured UVM testbenches and VIP suites.
Physical Implementation
Standard cell synthesis and place & route using industry-standard tools. Static timing analysis targets 1 GHz+ operation on standard foundry process nodes.
iNoCulator™ web tool generates NoC RTL directly from architectural exploration; no other EDA tool covers this step. SystemC, QEMU, and Questa flows take you from RTL to sign-off without leaving the SigIP ecosystem.
Launch iNoCulator →