IP you license.
Chiplets
you design.
PCIe Gen 6.x, CXL 3.x, and NoC IP: licensable standalone today. Or engage SignatureIP to design your full Compute, IO, and Memory Expander silicon to spec, assembled from the same blocks.
Every PCIe Gen 6.x Subsystem, CXL 3.x Subsystem, and NoC block in our standalone catalog is also a building block in every Compute, IO, and Memory Expander silicon engagement.
1. License the IP now.
2. Design the chiplet when you're ready to scale.
verified RTL
Microarchitected for PPA.
Every SignatureIP block is microarchitected from first principles to be modular, reusable, and PPA-optimized.
Low Power
→ Delivered by PCIe Gen 6.x and CXL 3.x
→ Power domains designed modularly at the microarchitecture level.
→ Active, standby, and retention states built into every IP block.
Optimal Latency + Throughput
→ Delivered by NoC topologies generated by iNoCulator™
High Performance
→ Backward compatible Gen 6 to Gen 1
→ 1 GHz operating frequency target on PCIe Gen 6.
→ CHI Rev E.b coherency without latency compromise.
Optimal Area
→ Modular, reusable microarchitecture eliminates redundancy across IP instances.
→ ATC, ATS, and DTI shared between PCIe Gen 6.x and CXL 3.x subsystems: one NoC attachment point for two protocols.
Design your NoC in the browser.
The only cloud-native NoC EDA tool. Set your targets. The tool designs the topology and generates the optimal C-Noc and NC-NOC topology generation. Configures for single-silicon monolithic SoCs and multi-silicon chiplet packages: the same tool serves both design motions.
- ✓Full sign-off flow. RTL feeds directly into Siemens Questa simulation.
- ✓Processor-agnostic. Arm CHI, RISC-V, and custom processor interfaces.
License IP today.
PCIe Gen 6.x Subsystem, CXL 3.x Subsystem, NoC, SysWare, Peripherals: standalone, ready.
Request datasheets →Commission a chiplet.
Compute, IO, Memory, or Transport: custom to your spec, assembled from SigIP blocks. Start the conversation.
Start chiplet design conversation →